`timescale 100ns / 100ps

                       
module tb_ModSynhGen
    (   output logic                    clk
        );
//*********************** КОНСТАНТЫ ****************************************************************

//*********************** СОЗДАНИЕ И ОПИСАНИЕ ПЕРЕМЕННЫХ *******************************************
    logic reset_n;
    
    logic       start;
    logic vldata, vrdata, vsample, vrsync, vlsync, vhdata, vhsync, vclamp;
    logic not_vldata;
//********************** БЛОК НЕПРЕРЫВНЫХ НАЗНАЧЕНИЙ ASSIGN ****************************************
    assign not_vldata = ~vldata;

//********************** ОПИСАНИЕ ПОДКЛЮЧАЕМЫХ БЛОКОВ ***********************************************

ModSynhGen
    #(  .vhdata_ns_p(2000),
        .sample_ns_p(1000),
        .vlsync_ns_p(1000),
        .col_p      (8),
        .row_p      (8)
    )
ModSynhGen_inst
    (   .reset_n    (reset_n),
        .clk        (clk),

        .start_i    (start),
        .exp_ns     (2000),
        .fill_ns    (20000),
        .vhsync_period_ns (1000),
        
        .vldata_o     (vldata),
        .vrdata_o     (vrdata), 
        .vsample_o    (vsample), 
        .vrsync_o     (vrsync), 
        .vlsync_o     (vlsync), 
        .vhdata_o     (vhdata), 
        .vhsync_o     (vhsync), 
        .vclamp_o     (vclamp)
    );
  
// ********************* БЛОКИ ИНИЦИАЛИЗАЦИИ *******************************************************
    initial begin
        reset_n = 0;
    #25  reset_n = 1;
    end
    
    initial begin        // CLK
        clk = 0;
        forever #5ns clk = ~clk;
    end
    
    initial begin        // CLK

        // repeat (50) begin
            start = 0;
            #50;
            start = 1;
            #50;
            start = 0;
        // end;
    end    
endmodule